The present invention relates to a method and/or architecture for fitting a design into a programmable logic device (PLD) generally and, more particularly, to a method and/or architecture for fitting a design into a PLD without additional latency.
Programmable logic devices (PLDs) can have multiple logic equations (i.e., EQN1 and EQN2), which need to be fit inside the PLD. The xe2x80x9cfittingxe2x80x9d of equations into the PLD can involve several stages such as (i) design creation (i.e., generation of a formal design), (ii) synthesis (i.e., translating the design into equations expressed in AND-OR form or other logical form more directly implementable in the PLD) and (iii) placement (i.e., allocating silicon resources in a PLD for the equations). After the synthesis step, each of the equations EQN1 and EQN2 typically has numerous inputs and multiple stages. The stages can be the result of a particular way the design is written and/or generated by the synthesis software. Furthermore, either because of inherent capacity limitation of the device, or artificial placement constraints (i.e., pin locking by the designer), the equations EQN1 and EQN2 typically have to be placed in the same final logic block. In this discussion a logic block is where the equation is partly or wholly implemented. However, the final logic block might not be able to accommodate the equations EQN1 and EQN2 (i.e., when the final stage logic block does not have enough input lines to fit the equations EQN1 and EQN2).
Referring to FIG. 1, a circuit 10 including a number of logic blocks 12a-12n is shown. The logic blocks 12 have inputs 14a-14n and outputs 16a-16n. The logic blocks 12a, 12c, 12d and 12n attempt to fit the equation EQN1. The logic blocks 12b, 12e, and 12n attempt to fit the equation EQN2. The circuit 10 attempts to place the equations EQN1 and EQN2 in the final logic block 12n. However, such a configuration is not possible, since the equation EQN2 is partly outside the logic block 12n. In particular, the design as generated by the software for the equations EQN1 and EQN2 exceeds the capacity of the logic block 12n as shown symbolically with the input 14n outside of the logic block 12n. Therefore, the design as generated by the synthesis software is non-functional. In another example, the circuit 10 can be synthesized without proper placement of one or more of the logic blocks 12, the outputs 16, etc. via conventional synthesis software.
Using conventional approaches, changes to make the circuit 10 functional must be made manually at the RTL level or above. Such changes are inconvenient and error prone. Furthermore, the changes are independently specified depending on particular software applications. Thus, the circuit 10 exhibits different behavior when switched to different software applications. The circuit 10 also adds undesired timing latency. Since latency is added to the equations EQN1 and EQN2, such an approach is too cumbersome to ensure correct function of the entire design. Additionally, designers do not have control over the nodal synthesis that leads to additional latency, which can make such change impossible.
Referring to FIG. 2, a circuit 20 including a number of logic blocks 22a-22d having inputs 24a-24n and outputs 26a-26n is shown. The implementation of the equation EQN1 is the same as that of FIG. 1 and is not shown. The logic blocks 22a, 22b, 22c and 22d fit the equation EQN2 (i.e., the logic block 22d contains all of the inputs 22b-22n). In limited circumstances, manual intervention can be used to solve problems encountered when insufficient inputs are allocated to logic blocks (i.e., by adding a latency stage via the logic block 22c). The circuit 20 reduces the number of inputs required for the last stage 22d of the equations EQN1 and EQN2. However, the additional latency stage 22c adds undesirable latency, cost, utilization and development time.
Synthesis software typically provides users with optimization options in the synthesis step. For example, users can specify a level of optimization and synthesized design size (i.e., number of nodes). The user options affect how the software synthesizes a design. For example, with lower nodal cost, the software will generate more stages for the equations EQN1 and EQN2 by adding either parallel or serial stages.
Referring to FIG. 3, a circuit 30 including a number of stages 32a-32i is shown. The circuit 30 is affected by user optimization synthesis features. Equations that are originally placed and functioning properly (i.e., EQN1 of the PLD 10) are altered (i.e., in the circuit 10, EQN1 has the two inputs 14s and 14t, while in the circuit 30, EQN1 has the three inputs 34s, 34t and 34u). Additionally, the circuit 30 does not fit the EQN2 (i.e., symbolically shown by the input 34n not placed in the logic block 32n). Even if the equations can now fit after alterations, because the equations are expanded, more resources are used in the PLD 30, resulting in higher utilization of the die space with no added functional value. Resources are wasted on the PLD 30. The user optimization synthesis features shown in PLD 30 do not provide precise control of resource allocation with regard to expansion and location. Additionally, since the circuit 30 implements a general expansion strategy, timing for the design 30 is changed.
It is generally desirable to have a method and/or architecture for PLD design fitting that (i) provides a simplified localized expansion placement technique without adding latency, (ii) reduces design cost and time, and/or (iii) minimizes die area.
The present invention concerns a method for placement and manipulation of logic equations of a device design, comprising the steps of (A) identifying one or more logic equations of the device design with placement problems, (B) identifying one or more candidate equations of the logic equations with placement problems, and (C) re-synthesizing the one or more logic blocks of the candidate equations without adding latency to the device design.
The objects, features and advantages of the present invention include providing a method and/or architecture for fitting a design into a PLD that may (i) be implemented without adding latency to the equation output, (ii) preserve design timing (iii) provide localized operations, (iv) provide more optimized device utilization, (v) conserve utilized die area, (vi) provide localized and controlled manipulation and expansion, (vii) be implemented without needing user intervention, (viii) protect valid equation design, (ix) be implemented on internal as well as external nodes, and/or (x) even out device logic placement.